Foreword
In design of personal computer automation, as bus line speed more and more piece, the ascendant ／ of chip drops the edge is steeper and steeper, sequential problem becomes more and more outstanding. Sequential problem is crucial in the design, especially as clock frequency rise, leave number to read the N that write a window effectively according to what transmit smaller and smaller, want to be inside very short time, make data signal conveys thoroughly from drive end sink, must undertake mathematical sequential calculation and analysis. In the meantime, the integrality of sequential and signal also is inseparable, good signal quality is the key that ensures sequential is stable. As a result of the reflection, signal quality problem that strings together faze to cause, very the deflection that Ding can bring sequential and disorder, bring about sequential surplus insufficient.
1The SPI interface of MC68332 and AT93C46
The hardware interface of MC68332 and serial memory AT93C46 is simpler, if pursue,1 is shown. Among them, the CS of MC68332, CLK(and MOSI foot are SPI output; MISO foot is SPI input.
2 sequential problem puts forward
Debugging the AT93C46 that batch appears to differ in the process, read data to be able to undertake correctly. But when keeping data, some batch are written correct, some criterion occurrence mistake. MC68332 and AT93C46SPI interface analyse below keep sequential chart (if the graph is shown 2 times) reach parameter (1) seeing a table.
Graph 2 in, TDIS amount to occupies set-up time, AT93C46 data manual asks its are the smallest the value is 10Ons; TDIH holds time for data, ask its are the smallest the value is 100ns.
In MC68332 manual, TDIS is the smallest the value is 5Ons, TDIH is the smallest the value is 50ns.
Set-up time of visible TDIS data is insufficient, the data that draws up in MC68332 that is to say still does not have stable circumstance to fall, the ascendant edge of SK clock has come. At this moment, the data with AT93C46 meeting not stable general undertakes locking up putting. Such, the data that the lock below major case collects is wrong.
3 sequential ask the problem is solved
Sequential surplus has two respects reason commonly not quite: It is parameter of each chip sequential does not match systematic itself; 2 it is signal integrality is differred, bring about sequential surplus to decrease. To solve the problem with data insufficient set-up time, enter the MISO data of the SPI interface of MC68332, MOSI data produces, CLK clock signal is received undertake into EPLD sequential is adjusted. The ascendant edge CLK signal backward translation, drop along forward translation, make build and hold time lengthen. Adjust in EPLD after build and holding time, the AT93C46 of any batch can read ／ correctly to write. Graph 3 with the graph 4 it is the undee figure that sequential adjusts around oscillograph respectively.
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