In the past 10 years, the design personnel of the whole world has discussed to use ASIC or the advantage that FPGA will come to realize digital electron to design. The flexibility of the performance dominant position that normally these discuss completely will custom-built IC and low power comsumption and FPGA and low NRE cost undertake comparative. The in advance in the team ought to be being designed in ASIC undertakes NRE invests, improve performance with utmost ground, reduce dimension and the cost when reducing large quantities of system of quantities to build? Perhaps design a team to should design what can only FPGA offer to have height to you can configure the function, end item that can you finish the job quickly for the market?
In fact, because high density spends IC to design the increasingly serious challenge that face, the notion above is not fundamental. As ASIC design personnel enters each new process, the design becomes more and more complex, the content of software increased, the time that place of test and verify needs is longer and longer. Recent research makes clear, the reason that the ASIC project of more than 60% fails is not sequential or the problem of power, however logistic or the function is wrong. For this, functional test and verify has become a the most crucial link in ASIC development cycle, normally most expend time. Discovery of more and more ASIC design personnel undertake through using FPGA functional prototype is designed can best satisfies a requirement. The ASIC part of more than 90% perhaps is flowing entirely piece before use FPGA to undertake archetypal design. Whether to because this problem is not,use ASIC or FPGA design. To satisfy the requirement of current market, most design team must both is used.
Method of test and verify
As a result of the serious demand to top-ranking chip, and mix as ASIC density the design is complex the blemish that spent addition brings, design personnel needs method of a kind of test and verify, so that can discover all flaw in complex chip design, and need finishs test and verify inside shorter time. Traditional software imitate method cannot satisfy a requirement.
The rate of need of method of test and verify that ASIC design personnel needs is rapid, price moderate, use easily, support is in dispersedly the hardware in whole design team and software blemish, and can run operating system and applied program immediately, use together with outside system component and interface easily.
Use FPGA to realize ASIC prototype, design personnel can every second runs vector of 10 thousand about a hundred tests, faster than traditional software imitate million times. Dominant position of this one performance can bring the software that designing cycle and systematic conformity level huge profit. Through moving in order to approach the rate of ASIC, FPGA prototype makes design personnel to be able to use hardware, shed video or network data to come test and verify is embedded software perhaps uses a program, check performance, discover the flaw that is hard to discover, if the design is involved embedded CPU, return the function that can design operating system of the test and verify before finishing in ASIC. Engineer of test and verify also can use indication data to undertake test and verify, and do not check platform with take time development.
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